Digital to Analog Converter using Binary Weighted Resistors R 2R

The R-2R ladder DAC which is a binary-weighted DAC that uses a repeating cascaded structure of resistor values R and 2R. This improves the precision due to the relative ease of producing equal valued-matched resistors (or current sources). However, wide converters perform slowly due to increasingly large RC-constants for each added R-2R link. The D/A converter using binary-weighted resistors is shown in the figure below. In the circuit, the op-amp is connected in the inverting mode. The op-amp can also be connected in the non-inverting mode. The circuit diagram represents a 4-digit converter. Thus, the number of binary inputs is four.

Circuit Diagram

Fig. 1

We know that, a 4-bit converter will have 2⁴ = 16 combinations of output. Thus, a corresponding 16 outputs of analog will also be present for the binary inputs.

Four switches from b0 to b3 are available to simulate the binary inputs: in practice, a 4-bit binary counter such as a 7493 can also be used.

Working

The circuit is basically working as a current to voltage converter.

1. b0 is closed
It will be connected directly  to the +5V.
Thus, voltage across R = 5V
Current through R = 5V/10kohm = 0.5mA
Current through feedback resistor, Rf = 0.5mA (Since, Input bias current, IB is negligible)
Thus, output voltage = -(1kohm)*(0.5mA) = -0.5V

2. b1 is closed, b0 is open
R/2 will be connected to the positive supply of the +5V.
Current through R will become twice the value of current (1mA) to flow through Rf.
Thus, output voltage also doubles.

3. b0 and b1 are closed
Current through Rf = 1.5mA
Output voltage = -(1kohm)*(1.5mA) = -1.5V

Thus, according to the position (ON/OFF) of the switches (bo-b3), the corresponding “binary-weighted” currents will be obtained in the input resistor. The current through Rf will be the sum of these currents. This overall current is then converted to its proportional output voltage. Naturally, the output will be maximum if the switches (b0-b3) are closed,

V0 = -Rf *([b0/R][b1/(R/2)][b2/(R/4)][b3/(R/8)]) 

Where each of the inputs b3, b2, b1, and b0 may either be HIGH (+5V) or LOW (0V).

The graph with the analog outputs versus possible combinations of inputs is shown below.

Fig. 2

The output is a negative going staircase waveform with 15 steps of -).5V each. In practice, due to the variations in the logic HIGH voltage levels, all the steps will not have the same size. The value of the feedback resistor Rf changes the size of the steps. Thus, a desired size for a step can be obtained by connecting the appropriate feedback resistor. The only condition to look out for is that the maximum output voltage should not exceed the saturation levels of the op-amp. Metal-film resistors are more preferred for obtaining accurate outputs.

Disadvantages

If the number of inputs (>4) or combinations (>16) is more, the binary-weighted resistors may not be readily available. This is why; R and 2R method is more preferred as it requires only two sets of precision resistance values.

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Transistor Schmitt Trigger Oscillator

The Schmitt Trigger oscillator below employs 3 transistors, 6 resistors and a capacitor to generate a square waveform. Pulse waveforms can be generated with an additional diode and resistor (R6). Q1 and Q2 are connected with a common emitter resistor (R1) so that the conduction of one transistor causes the other to turn off. Q3 is controlled by Q2 and provides the squarewave output from the collector.

In operation, the timing capacitor charges and discharges through the feedback resistor (Rf) toward the output voltage. When the capacitor voltage rises above the base voltage at Q2, Q1 begins to conduct, causing Q2 and Q3 to turn off, and the output voltage to fall to 0. This in turn produces a lower voltage at the base of Q2 and causes the capacitor to begin discharging toward 0. When the capacitor voltages falls below the base voltage at Q2, Q1 will turn off causing Q2 and Q3 to turn on and the output to rise to near the supply voltage and the capacitor to begin charging and repeating the cycle. The switching levels are established by R2,R4 and R5. When the output is high, the voltage at the base of Q2 is determined by R4 in parallel with R5 and the combination in series with R2. When the output is low, the base voltage is set by R4 in parallel with R2 and the combination in series with R5. This assumes R3 is a small value compared to R2. The switching levels will be about 1/3 and 2/3 of the supply voltage if the three resistors are equal (R2,R4,R5).

There are many different combinations of resistor values that can be used. R3 should low enough to pull the output signal down as far as needed when the circuit is connected to a load. So if the load draws 1mA and the low voltage needed is 0.5 volts, R3 would be 0.5/.001 = 500 ohms (510 standard). When the output is high, Q3 will supply current to the load and also current through R3. If 10 mA is needed for the load and the supply voltage is 12, the transistor current will be 24 mA for R3 plus 10 mA to the load = 34 mA total. Assuming a minimum transistor gain of 20, the collector current for Q2 and base current for Q3 will be 34/20 = 1.7 mA. If the switching levels are 1/3 and 2/3 of the supply (12 volts) then the high level emitter voltage for Q1 and Q2 will be about 7 volts, so the emitter resistor (R1) will be 7/0.0017 = 3.9K standard. A lower value (1 or 2K) would also work and provide a little more base drive to Q3 than needed. The remaining resistors R2, R4, R5 can be about 10 times the value of R1, or something around 39K.

The combination of the capacitor and the feedback resistor (Rf) determines the frequency. If the switching levels are 1/3 and 2/3 of the supply, the half cycle time interval will be about 0.693*Rf*C which is similar to the 555 timer formula. The unit I assembled uses a 56K and 0.1 uF cap for a positive time interval of about 3.5 mS. An additional 22K resistor and diode were used in parallel with the 56K to reduce the negative time interval to about 1 mS.

In the diagram, T1 represents the time at which the capacitor voltage has fallen to the lower trigger potential (4 volts at the base of Q2) and caused Q1 to switch off and Q2 and Q3 to switch on. T2 represents the next event when the capacitor voltage has risen to 8 volts causing Q2 an Q3 to turn off and Q1 to conduct. T3 represents the same condition as T1 where the cycle begins to repeat. Now, if you look close on a scope, you will notice the duty cycle is not exactly 50% This is due to the small base current of Q1 which is supplied by the capacitor. As the capacitor charges, the E/B of Q1 is reverse biased and the base does not draw any current from the capacitor so the charge time is slightly longer than the discharge. This problem can be compensated for with an additional diode and resistor as shown (R6) with the diode turned around the other way. 

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