Digital to Analog Converter using Binary Weighted Resistors R 2R

The R-2R ladder DAC which is a binary-weighted DAC that uses a repeating cascaded structure of resistor values R and 2R. This improves the precision due to the relative ease of producing equal valued-matched resistors (or current sources). However, wide converters perform slowly due to increasingly large RC-constants for each added R-2R link. The D/A converter using binary-weighted resistors is shown in the figure below. In the circuit, the op-amp is connected in the inverting mode. The op-amp can also be connected in the non-inverting mode. The circuit diagram represents a 4-digit converter. Thus, the number of binary inputs is four.

Circuit Diagram

Fig. 1

We know that, a 4-bit converter will have 2⁴ = 16 combinations of output. Thus, a corresponding 16 outputs of analog will also be present for the binary inputs.

Four switches from b0 to b3 are available to simulate the binary inputs: in practice, a 4-bit binary counter such as a 7493 can also be used.

Working

The circuit is basically working as a current to voltage converter.

1. b0 is closed
It will be connected directly  to the +5V.
Thus, voltage across R = 5V
Current through R = 5V/10kohm = 0.5mA
Current through feedback resistor, Rf = 0.5mA (Since, Input bias current, IB is negligible)
Thus, output voltage = -(1kohm)*(0.5mA) = -0.5V

2. b1 is closed, b0 is open
R/2 will be connected to the positive supply of the +5V.
Current through R will become twice the value of current (1mA) to flow through Rf.
Thus, output voltage also doubles.

3. b0 and b1 are closed
Current through Rf = 1.5mA
Output voltage = -(1kohm)*(1.5mA) = -1.5V

Thus, according to the position (ON/OFF) of the switches (bo-b3), the corresponding “binary-weighted” currents will be obtained in the input resistor. The current through Rf will be the sum of these currents. This overall current is then converted to its proportional output voltage. Naturally, the output will be maximum if the switches (b0-b3) are closed,

V0 = -Rf *([b0/R][b1/(R/2)][b2/(R/4)][b3/(R/8)]) 

Where each of the inputs b3, b2, b1, and b0 may either be HIGH (+5V) or LOW (0V).

The graph with the analog outputs versus possible combinations of inputs is shown below.

Fig. 2

The output is a negative going staircase waveform with 15 steps of -).5V each. In practice, due to the variations in the logic HIGH voltage levels, all the steps will not have the same size. The value of the feedback resistor Rf changes the size of the steps. Thus, a desired size for a step can be obtained by connecting the appropriate feedback resistor. The only condition to look out for is that the maximum output voltage should not exceed the saturation levels of the op-amp. Metal-film resistors are more preferred for obtaining accurate outputs.

Disadvantages

If the number of inputs (>4) or combinations (>16) is more, the binary-weighted resistors may not be readily available. This is why; R and 2R method is more preferred as it requires only two sets of precision resistance values.

Read more

Build a Simple Digital Electronic Lock Circuit Diagram

Build a Simple Digital Electronic Lock Circuit Diagram. This is a Build a Simple Digital Electronic Lock Circuit Diagram. The digital lock shown below uses 4 common logic ICs to allow controlling a relay by entering a 4 digit number on a keypad. The first 4 outputs from the CD4017 decade counter (pins 3,2,4,7) are gated together with 4 digits from a keypad so that as the keys are depressed in the correct order, the counter will advance.

Simple Digital Electronic Lock Circuit Diagram

As each correct key is pressed, a low level appears at the output of the dual NAND gate producing a high level at the output of the 8 input NAND at pin 13. The momentary high level from pin 13 activates a one shot circuit which applies an approximate 80 millisecond positive going pulse to the clock line (pin 14) of the decade counter which advances it one count on the rising edge.

A second monostable, one shot circuit is used to generate an approximate 40 millisecond positive going pulse which is applied to the common point of the keypad so that the appropriate NAND gate will see two logic high levels when the correct key is pressed (one from the counter and the other from the key). The inverted clock pulse (negative going) at pin 12 of the 74C14 and the positive going keypad pulse at pin 6 are gated together using two diodes as an AND gate (shown in lower right corner). The output at the junction of the diodes will be positive in the event a wrong key is pressed and will reset the counter.

When a correct key is pressed, outputs will be present from both monostable circuits (clock and keypad) causing the reset line to remain low and allowing the counter to advance. However, since the keypad pulse begins slightly before the clock, a 0.1uF capacitor is connected to the reset line to delay the reset until the inverted clock arrives. The values are not critical and various other timing schemes could be used but the clock signal should be slightly longer than the keypad pulse so that the clock signal can mask out the keypad and avoid resetting the counter in the event the clock pulse ends before the keypad pulse.

The fifth output of the counter is on pin 10, so that after four correct key entries have been made, pin 10 will move to a high level and can be used to activate a relay, illuminate an LED, ect. At this point, the lock can be reset simply by pressing any key.

The circuit can be extended with additional gates (one more CD4011) to accept up to a 8 digit code. The 4017 counting order is 3 2 4 7 10 1 5 6 9 11 so that the first 8 outputs are connected to the NAND gates and pin 9 would be used to drive the relay or light. The 4 additional NAND gate outputs would connect to the 4 remaining inputs of the CD4068 (pins 9,10,11,12). The circuit will operate from 3 to 12 volts on 4000 series CMOS but only 6 volts or less if 74HC parts are used. The circuit draws very little current (about 165 microamps) so it could be powered for several months on 4 AA batteries assuming only intermittent use of the relay.

Sourced By : Streampowers

Read more